VHDL Testbench Generator 16 FEB 2013
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Date Added: |
Apr 23, 2013 03:37 AM |
Publisher's Description: |
This utility has been developed primarily for those who are learning VHDL and want to do a quick validation of their design(s). However, this tool can also be used for design/DV purpose. One such occasion could be when the RTL owner needs to compile, elaborate and run the 0th time simulation. The 0th time simulation is required in order to ensure that the simulation bringup is correct. There are certain design issues which does not show up until the design gets simulated at the 0th time.
You need Java JRE 1.6.x or above to use all these utilities.
How to run this tool ?
Download and extract the tar file and follow the simple steps/commands to generate the testbench. There are few examples which can be used as reference. Here is one example-
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Documentation: |
http://www.edautils.com/VHDLTBGen.html |
Last Download: |
Mar 19, 2024 01:17 AM
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Downloads: |
237 |
OS: |
Windows |
Rating: |
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